Over 30 years, semiconductor devices have been scaled down according to Moore's Law. The feature size of semiconductor integrated circuit continuously reduces and the level of integration continuously increases. As the technology node enters the deep sub-micron area, such as 100 nm or less, even less than 45 nm or less, traditional field-effect transistors (FETs), i.e., planar FETs, begin to be subject to limitations of various basic physical laws, challenging the scaled down prospect. Many FETs with new structures are developed to meet the actual needs, wherein FinFET is a new structural device with a great scaled-down potential.
A FinFET, i.e., a fin field-effect transistor, is a multi-gate semiconductor device. Due to the unique characteristics in structure, FinFET becomes a promising device beyond 22 nm technology node. Referring to FIG. 1, a FinFET comprises a Fin 2 perpendicular to the substrate 1. The Fin is formed as a fin-shaped semiconductor column. Unlike a conventional planar FET, the channel region of the FinFET is located within the Fin. A gate dielectric layer 3 and a gate 4 surround Fin at the side surfaces and the top surface to form a gate having at least two sides, i.e., a gate located on both side surfaces and the top surface of Fin, thereby gaining better control over the channel region. It becomes possible to provide “fully depleted” type operation. The two ends of the Fin2 that are not surrounded by gate 4 are source/drain region 5. By controlling the thickness of the Fin2, FinFET exhibits excellent characteristics: better short channel effect suppression, better sub-threshold slope, low off-state current, elimination of the floating body effect, lower operating voltage, and more advantageous to be scaled-down. In order to obtain a greater driving force, a plurality of parallel semiconductor fins can be controlled by one gate. Referring to FIG. 2, a plurality of Fins 2 are controlled by the one gate 4, wherein the obtained FinFET has greater driving capability so that the circuits have better performance. FIG. 3 is a microphotograph of a FinFET with a plurality of parallel semiconductor fins.
Due to the shape of the semiconductor fins, the surface area of the top of Fin is very small. Thus, the contact area of the FinFET source/drain region used to form a contact plug is very small. Meanwhile, it is more difficult to form a source/drain region contact by a self-aligned process since the contact area is small. Due to the small contact area and the process variation, the FinFET source/drain region contact plug formed by self-aligned metal materials has a large contact resistance, which will result in large parasitic capacitance and significantly reduce the speed of the entire circuit. Therefore, there is a need to provide a method of manufacturing a FinFET to solve the above problem with the proviso that the inherent advantages of FinFET are ensured.